The present invention generally relates to semiconductor memory devices and methods of testing the same, and more particularly to a semiconductor memory device having a testing function and a method of testing such a semiconductor memory device.
As the integration density of semiconductor memory devices improve, the time required to test the produced memory chips increases considerably. The main reason for the considerable increase in the testing time is due to the fact that the operating speed of the memory has not been improved considerably relative to the increase in the number of bits. The testing time can be determined from "the operating time per bit".times."the number of bits".times."the coefficient which is determined by the test pattern"/"number of bits tested simultaneously in parallel". As a result, the cost involved in testing the memory chip makes up a large percentage of the cost of the memory chip.
The test is used to detect and exclude the bits which are clearly defective. But the test is also used to detect and exclude bits which are unstable and become defective depending on the conditions. The testing time required to detect the latter type of bits is considerably long. However, because the test must be completed within a limited time, it is difficult in actual practice to take a sufficiently long time to test each bit.
Conventionally, there is a method of testing unstable bits of a dynamic random access memory (DRAM) by reducing the charge of the memory cell by some means, so as to forcibly reduce the output voltage of the memory cell from the regular value. By forcibly reducing the output voltage of the memory cell, the DRAM is put into a state where an error is more likely to occur so that it becomes possible to correctly detect a defect which would otherwise be considered normal during a normal test cycle. Such an error is more likely to occur in a memory cell which has a small capacitance due to some abnormal cause, a memory cell in which the pn junction and the transistor easily leak thereby causing a quick decrease in the charge, and a sense amplifier which has a poor sensitivity due to some abnormality. Particularly, the output voltage of the memory cell can be forcibly reduced by setting the voltage of a cell plate (counter electrode of the stacked capacitor) of the DRAM cell to different values for the write and read operations, so as to modulate the charge stored in the DRAM cell.
For example, when writing a data "1" into the memory cell and thereafter reading out this data, the apparent stored charge is reduced if the cell plate voltage is reduced during the read operation when compared to that during the write operation. In this manner, it is possible to forcibly reduce the output voltage of this data "1". Particularly, when the write operation is made by setting the cell plate voltage V.sub.CP to 2.5 V and the bit line voltage V.sub.BL to 5 V, the cell voltage V.sub.C becomes V.sub.C =V.sub.BL -V.sub.CP =2.5 V and the charge Q stored in the memory cell is a product of this cell voltage V.sub.C and the capacitance C of the memory cell. When the read operation is made by setting the cell plate voltage V.sub.CP to V.sub.CP =1.5 V, the bit line voltage V.sub.BL becomes V.sub.BL =V.sub.CP +V.sub.C =4 V which is 1 V lower than the bit line voltage of 5 V which is used when making the normal read operation at V.sub.CP =2.5.
The charge within the memory cell having a poor charge holding characteristic decreases after the level "1" is written therein, and according to the above described method, the decrease of this level "1" is made more conspicuous by forcibly reducing the output voltage of the memory cell, thereby making it possible to detect the unstable memory cell as a defective memory cell.
The method of reducing the cell plate voltage during the read operation can detect the memory cell which has an unstable level "1". However, in order to detect the memory cell which has an unstable level "0", it is necessary to increase the cell plate voltage during the read operation compared to that during the write operation. Generally, when the cause of the defective memory cell is due to the pn junction leak within the memory cell, only the decrease of the level "1" occurs and there is no modulation of the level "0". For this reason, it is sufficient to simply reduce the cell plate voltage when detecting the defective memory cell if only the storage electrode and the capacitor are taken into consideration. However, in the case of a memory cell such that the bit line and the word line are becoming short-circuited, the defective bit is caused by the modulation of the level "0". In other words, if the selected memory cell holds the level "0" and the word line and the bit line are short-circuited when reading from this selected memory cell, the bit line voltage is pulled towards the high level via the word line, and the defect is detected because the read data appears as if the level "1" were read.
Therefore, in order to guarantee no leak of the memory cell for both the level "1" and the level "0", the modulation of the cell plate voltage must be made for the level "1" and for the level "0" and the test must be carried out twice. The above leak of the memory cell refers to a failure other than an evident short-circuit which can be simply detected, such that a current leak occurs via a high resistance thereby causing an unstable operation of the memory cell. If the test is not carried out twice, it becomes necessary to employ a production process which guarantees that no leak will occur between the bit line and the word line. But such a production process generally requires the memory cells to have a relatively large size in order to facilitate the production, and as a result, the chip size becomes large and the production cost increases. On the other hand, the cost of the test increases if the test is carried out twice.
According to the conventional method of detecting the bits with the unstable operation (hereinafter referred to as "screening"), the cell plate voltage must be varied to detect the instability (leak relates to the storage electrode and the capacitor) with respect to the data "1" and to detect the instability (leak between the bit line and the word line) with respect to the data "0" for each cycle in the case of a data pattern such as "marching" which is used when the special operation of reducing the output voltage of the memory cell is made during read and write operations which are carried out alternatively. However, in actual practice, the cell plate voltage cannot be varied at a sufficiently high speed which follows the minimum operation cycle because of the relatively large cell plate capacitance. For this reason, there is a problem in that the required testing time is long.